Analysis and design of a new structure for 10-bit 350ms/s pipeline analog to digital converter
| Autor | Arash Rezapour - Mohammad Bagher Tavakoli - Farbod Setoudeh |
| Cargo | Department of Electronic, Arak Branch, Islamic Azad University, Arak, Iran. - Department of Electronic, Arak Branch, Islamic Azad University, Arak, Iran. Corresponding. Author Email: *m-tavakoli@iau-arak.ac.ir. - Department of Electronic, Arak University of Technology, Arak, Iran |
| Páginas | 301-328 |
Periódico do Núcleo de Estudos e Pesquisas sobre Gênero e Direito
Centro de Ciências Jurídicas - Universidade Federal da Paraíba
V. 8 - Nº 03 - Ano 2019
ISSN | 2179-7137 | http://periodicos.ufpb.br/ojs2/index.php/ged/index
301
ANALYSIS AND DESIGN OF A NEW STRUCTURE FOR 10-BIT
350MS/S PIPELINE ANALOG TO DIGITAL CONVERTER
Arash Rezapour
1
Mohammad Bagher Tavakoli
2
Farbod Setoudeh
3
Abstract: A 10-bit pipelined Analog to
Digital converter is proposed in this paper
with using 0.18 µm TSMC technology. In
this paper, a new structure is proposed to
increase the speed of the pipeline analog to
digital convertor. So at the first stage is not
used the amplifier and instead the buffer is
used for data transfer to the second stage.
The speed of this converter is 350MS/s. An
amplifier circuit with accurate gain of 6 and
a very accurate unit gain buffer circuit that
are open loop with a new structure were
used. In this Converter, the first 3 bits are
extracted simultaneously with sampling.
The proposed analog-to-digital converter
was designed with the total power
consumption 75mW using power supply of
1.8v.
Keywords: Analog to Digital Pipeline,
Comparator, Amplifiers, Buffer
1
Department of Electronic, Arak Branch, Islamic Azad University, Arak, Iran.
2
Department of Electronic, Arak Branch, Islamic Azad University, Arak, Iran. Corresponding
Author Email: *m-tavakoli@iau-arak.ac.ir.
3
Department of Electronic, Arak University of Technology, Arak, Iran
Introduction
Today Analog signals have been
replaced by digital signals. Analog-to-digital
convertor (ADC) play a key role in today's
modern telecommunications [1-5].So far,
various structures have been proposed for
the implementation of analog-to-digital
converters, which have different
specifications. One of these structures is
pipeline analog to digital converter. The
purpose of this design is to improve speed.
In this structure, there is an
amplifier as well as a sample and hold circuit
between the blocks of each stage. At the end
of each cycle, part of the digital output code
is extracted and an extra signal is transferred
to the next block. The speed of this structure
is independent of the number of stages used.
This structure, like other sub-ranging
structures, can achieve high precision using
low hardware [6-15].As a result, the output
Periódico do Núcleo de Estudos e Pesquisas sobre Gênero e Direito
Centro de Ciências Jurídicas - Universidade Federal da Paraíba
V. 8 - Nº 03 - Ano 2019
ISSN | 2179-7137 | http://periodicos.ufpb.br/ojs2/index.php/ged/index
302
of all comparators whose reference voltage
is smaller than the sampled signal is one, and
vice versa the output of all comparators
whose reference voltage is larger than the
sampled signal is zero. Given that these
comparisons are performed in a completely
parallel manner, and the speed of this type of
convertor depends only on the comparators
or the sampler circuit, the flash analogue to
digital convertor can have very high speeds.
But the two major problems with this
structure are the sensitivity of the
comparators to the offset input and a lot of
hardware has been used in it, because, as
mentioned, it requires 2n-1 comparator. On
the other hand a many number of
comparators increase the scale and power
consumption. Therefore, a convertor with
this structure requires high levels and high
power to achieve high precision. Hence,
these structures are not actually used to build
10-bit convertor s because they cost more
and require high power consumption and
more space. Another structure used is the
Two Step flash convertor. The basic block of
this convertor is the same type of flash
convertor. This structure is made up of two
successive flash memory modules [16-17].
The mode of operation of this type of
convertor is such that on the first floor, the
bits of the signal are detected. Then a digital-
to-analog convertor returns the equivalent of
the analog bits of value. This amount is
reduced from the original signal value and
the remainder enters the second stage. In this
stage, low-value bits are extracted.
Obviously, the conversion time for this
convertor is long as compared with the
simple flash type convertor, but instead uses
a smaller number of comparators, which
means less than 2n/2×2 comparators. By
breaking the conversion process to several
steps, the number of comparators is reduced.
But the conversion time increases. The
Subranging converter has several processing
steps, which are specified by the number of
stages [18-21]. Structures, it is necessary to
have a structure that has very high speed and
acceptable power consumption.
In reference [1], a 10-bit ADC is
proposed with a power consumption of
19.7mW, which has a low speed of
100MS/s, voltage supply is 1.8v in 0.18µm
technology, In Reference [1], for design 10-
bit Pipeline Analog to Digital it used two-
stage, and has used two flashes (3bits and
4bits) at each stage but in this 10-bit Pipeline
Analog to Digital proposed we used one
flashes ( just 4bits) at each stage, on the
stage1 is not used the gain stage, Instead, it
used buffer, That's an advantage and makes
the power consumption decreases and the
converter speed increases, On the other hand
to speed up on the stage2 we used open loop
amplifier, also comparator designed is able
to eliminate unwanted offsets and detect the
smallest amount of input. In reference [2],
pipeline ADC is designed with a low speed
and high power consumption of 136mW, in
other hand, the voltage supply is high. In
Para continuar a ler
PEÇA SUA AVALIAÇÃO